? 2002 quicklogic corporation www.quicklogic.com ? preliminary 1 ? device highlights flexible programmable logic 0.18 m six layer metal cmos process 1.8/2.5/3.3 v drive capable i/o 1,536 logic cells 320,640 max system gates up to 310 i/o pins embedded dual port sram twenty-four 2,304-bit dual port high performance sram blocks 55,300 ram bits ram/rom/fifo wiza rd for automatic configuration configurable and cascadable programmable i/o high performance enhanced i/o (eio)? less than 3 ns tco programmable slew rate control programmable i/o standards: lvttl, lvcmos, pci, gtl+, sstl2, and sstl3 eight independent i/o banks three register configurations: input, output, and output enable advanced clock network nine global clock networks: one dedicated eight programmable 20 quad-net networks?five per quadrant 16 i/o controls?two per i/o bank four phase locked loops embedded computational units 12 ecus provide integrat ed multiply, add, and accumulate functions. figure 1: ql6325-e eclipse-e block diagram embedded ram blocks pll pll fabric 12 embeded computational units embedded ram blocks pll pll fpga combining perform ance, density, and embedded ram ql6325-e eclipse-e data sheet
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 2 electrical specifications ac characteristics* *at v cc = 2.5 v, ta = 25 c, worst case corner, speed grade = -7 (k = 1.16) the ac specifications are provided from table 1 to table 10 . logic cell diagrams and waveforms are provided from figure 2 to figure 15 . figure 2: eclipse-e logic cell table 1: logic cells symbol parameter value logic cells min max t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output - 0.257 ns t su setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.22 ns - t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t co clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. - 0.255 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns - t cwlo clock low time: required minimum time that the clock stays low 0.46 ns - t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) - 0.18 ns
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 3 figure 3: logic cell flip-flop figure 4: logic cell flip-flop timings?first waveform t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) - 0.09 ns t sw set width: time that the set signal remains high/low 0.3 ns - t rw reset width: time that the reset signal remains high/low 0.3 ns - table 1: logic cells (continued) symbol parameter value logic cells min max set d clk reset q set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 4 figure 5: logic cell flip-flop timings?second waveform figure 6: eclipse-e global clock structure table 2: eclipse-e clock delay clock source parameters clock performance global dedicated logic cells (internal) clock signal generated internally 1.51 ns (max) clock pad clock signal generated externally 2.06 ns (max) 1.73 ns (max) clk d q t su t hl t co quad net
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 5 figure 7: global clock structure schematic figure 8: ram module table 3: eclipse-e global clock delay clock segment parameter value min max t pgck a a. when using a pll, t pgck and t bgck are effectively zero due to delay adjustment by phase locked loop. global clock pin delay to quad net - 1.34 ns t bgck global clock tree delay (quad net to flip-flop) - 0.56 ns programmable clock external clock global clock buffer global clock t pgck t bgck clock select wa wd we wclk re rclk ra rd ram module [9:0] [17:0] [9:0] [17:0] asyncrd
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 6 figure 9: ram cell sy nchronous write timing table 4: ram cell synchronous write timing symbol parameter value ram cell synchronous write timing min max t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.675 ns - t hwa wa hold time to wclk: time the write address must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.654 ns - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.623 ns - t hwe we hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 4.38 ns t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 7 figure 10: ram cell synchronous & asynchronous read timing table 5: ram cell synchronous & asynchronous read timing symbol ram cell synchronous read timing value parameter min max t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.686 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.243 ns - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 ns - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 4.38 ns ram cell asynchronous read timing r pdrd ra to rd: time between when the read address is input and when the data is output - 2.06 ns t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 8 figure 11: eclipse-e cell i/o figure 12: eclipse-e input register cell e r q d r q e r q d + - pad output enable register output register input register d pad t isu t sid + - q e d r
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 9 table 6: input register cell symbol parameter: input register cell only value min max t isu input register setup time: the time the synchronous input of the flip-flop must be stable before the active clock edge 2.50 ns - t ihl input register hold time: the time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns - t ico input register clock-to-out: the time taken by the flip-flop to output after the active clock edge - 1.08 ns t irst input register reset delay: the time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low) - 0.99 ns t iesu input register clock enable setup time: the time ?enable? must be stable before the active clock edge 0.37 ns - t ieh input register clock enable hold time: the time ?enable? must be stable after the active clock edge 0 ns - table 7: standard input delays symbol parameter value standard input delays to get the total input dela y add this delay to tisu min max t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.34 ns t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.42 ns t sid (lvcmos18) lvcmos18 input delay: low voltage cmos for 1.8 v applications - - t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.68 ns t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.55 ns t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.61 ns
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 10 figure 13: eclipse-e input register cell timing figure 14: eclipse-e output register cell r clk d q isu ihl ico iesu ieh irst e t t t t t t pad output register
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 11 figure 15: eclipse-e output register cell timing table 8: eclipse-e output register cell symbol parameter value output register cell only min max t outlh output delay low to high (90% of h) - 0.40 ns t outhl output delay high to low (10% of l) - 0.55 ns t pzh output delay tri-state to high (90% of h) - 2.94 ns t pzl output delay tri-state to low (10% of l) - 2.34 ns t phz output delay high to tri-state - 3.07 ns t plz output delay low to tri-state - 2.53 ns t cop clock-to-out delay (does not include clock tree delays) - 3.15 ns (fast slew) 10.2 ns (slow slew) table 9: output slew rates @ v ccio = 3.3 v fast slew slow slew rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns table 10: output slew rates @ v ccio = 2.5 v fast slew slow slew rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 12 table 11: output slew rates @vccio = 1.8 v fast slew slow slew rising edge - v/ns - v/ns falling edge - v/ns - v/ns
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 13 dc characteristics the dc specifications are provided in table 12 through table 14 . table 12: absolute maximum ratings parameter value parameter value v cc voltage -0.5 v to 3.6 v dc input current 20 ma v ccio voltage -0.5 v to 4.6 v esd pad protection 2000 v inref voltage 2.7 v leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to v ccio +0.5 v laminate package (bga) storage temperature -55 c to + 125 c latch-up immunity 100 ma table 13: operating range symbol parameter military industrial commercial unit min max min max min max v cc supply voltage 2.3 2.7 2.3 2.7 2.3 2.7 v v ccio i/o input tolerance voltage 1.62 3.6 1.62 3.6 1.62 3.6 v ta ambient temperature -55 -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -6 speed grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a -7 speed grade 0.42 1.27 0.43 1.19 0.46 1.16 n/a table 14: dc characteristics symbol parameter conditions min max units i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd -10 10 a c i input capacitance a a. capacitance is sample tested only. clock pins are 12 pf maximum. --8pf i os output short circuit current b b. only one output at a time. dura tion should not exceed 30 seconds. v o = gnd v o = v cc -15 40 -180 210 ma ma i cc d.c. supply current c c. for -6/-7 commercial grad e devices only. maximum i cc is 15 ma for all industrial grade devices, and 25 ma for all military grade devices. v i, v o = v ccio or gnd - 10 ma i ccio d.c. supply current on v ccio - 0 2 ma i ccio (dif) d.c. supply current on v ccio for differential i/o ---ma i ref d.c. supply current on inref - -10 10 a i pd pad pull-down (programmable) v ccio = 3.6 v - 150 a
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 14 embedded computational unit (ecu) traditional programmable logic ar chitectures do not implement arithmetic functions efficiently or effectively?these functions require high logic cell usage while garnering only moderate performance results. the ql6325-e architecture allows for functionality above and be yond that achievable using programmable logic devices. by embedding a dyna mically reconfigurable computational unit, the ql6325-e device can address various arithmetic fu nctions efficiently. th is approach offers greater performance than tradit ional programmable logic implementations. the embedded block is implemented at the transistor level as shown in figure 16 . figure 16: ecu block diagram the 12 ql6325-e ecu blocks are placed next to the sram circuitry for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. twelve 8-bit multiply-accumulate (mac) functions can be implemente d per cycle for a total of 1.2 billion macs when clocked at 100 mhz. additiona l mac functions can be implemented in the programmable logic. the modes for the ecu block are dynamically re -programmable through the programmable logic as shown in table 15 . a[0:15] b[0:15] sign2 sign1 cin s1 s2 s3 a b c d 3-4 decoder 8-bit multiplier 17 inc. cout 16-bit adder 17-bit register 2-1 mux 2-1 mux 3-1 mux q[0:16] clk reset dq 00 01 10 a[0:7] a[8:15]
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 15 table 15: ecu mode select criteria table 16. instruction operation ecu performance a , -7 wcc b a. t pd , t su and t co do not include routing paths in/out of the ecu block. b. timing numbers represent -7 worst case commercial conditions. s1 s2 s3 t pd t su t co 0 0 0 multiply 6.57 ns max 0 0 1 multiply-add 8.84 ns max 0 1 0 accumulate c c. internal feedback path in ecu restricts max clk frequency to 238 mhz. 3.91 ns min 1.16 ns max 0 1 1 add 3.14 ns max 1 0 0 multiply (registered) d d. b [15:0] set to zero. 9.61 ns min 1.16 ns max 1 0 1 multiply- add (registered) 9.61 ns min 1.16 ns max 1 1 0 multiply - accumulate 9.61 ns min 1.16 ns max 1 1 1 add (registered) 3.91 ns min 1.16 ns max
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 16 phase locked loops (plls) instead of requiring extra components, designer s simply need to instantiate one of the pre- configured models described in this section and listed in table . the quicklogic built-in plls support a wider range of frequencies than many other plls. also, quic klogic plls can be cascaded to support different rang es of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming cl ock frequency. most impo rtantly, they achieve a very short clock-to-out ti me?generally less than 3 ns. this lo w clock-to-out time is achieved by the pll subtracting the clock tree delay through the feedback path , effectively making the clock tree delay zero. figure 17 illustrates a typical quicklogic fpga pll. figure 17: pll block f in represents a very stable high-frequency input cl ock and produces an accu rate signal reference. this signal can either bypass the pll entirely, thus entering the clock tree di rectly, or it can pass through the pll itself. within the pll, a voltage-controlled oscillator (vco) is added to the circuit. the external f in signal and the local vco form a control loop. the vco is multiplied or divided down to the reference frequency, so that a phase dete ctor (the crossed circle in figure 17 ) can compare the two signals. if the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through th e charge pump and loop filter ( figure 17 ). the charge pump generates an error voltage to bring the vco back into alignment and the loop filter removes any high frequency noise before the error voltage en ters the vco. this new vco signal enters the clock tree to drive the chip's circuitry. f out represents the clock signal that emerges from the output pad (the output signal pllpad_out is explained in table 18 ). this clock signal is mean ingful only when the pll is configured for external use; otherwise, it remains in high z state, as shown in the post-simulation waveform. vco filter fin fout + - 1st quadrant 2nd quadrant 3rd quadrant 4th quadrant clock tree frequency divide frequency multiply 1 . _ . 2 . _ . 4 . _ . 4 . _ . 2 . _ . 1 . . _ pll bypass
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 17 most quicklogic products c ontain four plls, one to be used in each quadrant. the pll presented in figure 17 controls the clock tree in the fourth quadrant of its fpga. as previously noted, quicklogic plls compensate for the additional delay created by the clock tree itself by subtracting the clock tree dela y through the feedback path. for more specific informatio n on the phase locked loops, please refer to quicklogic application note 58. pll modes of operation quicklogic plls have eight modes of operation, based on the input frequency and desired output frequency? table 17 indicates the features of each mode. table 17: pll mode frequencies pll model output frequency input frequency range a a. the input frequency can range from 16 mhz to 250 mhz, while output frequency ranges from 25 mhz to 250 mhz. when you add plls to your top-level design , be sure that the pll mode matches your desired inpu t and output frequencies. output frequency range pll_hf b b. hf stands for high frequency and lf stands for low frequency. same as input frequency 66 mhz?150 mhz 66 mhz?150 mhz pll_lf same as input frequency 25 mhz?133 mhz 25 mhz?133 mhz pll_mult2hf 2 input frequency 50 mhz?125 mhz 100 mhz?250 mhz pll_mult2lf 2 input frequency 16 mhz?50 mhz 32 mhz?100 mhz pll_div2hf 1/2 input frequency 100 mhz?250 mhz 50 mhz?125 mhz pll_div2lf 1/2 input frequency 50 mhz?100 mhz 25 mhz?50 mhz pll_mult4 4 input frequency 16 mhz?40 mhz 64 mhz?160 mhz pll_div4 1/4 input frequency 100 mhz?300 mhz 25 mhz?75 mhz
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 18 pll signals table 18 summarizes the key signals in quicklogic?s plls. table 18: pll signals signal name description pllclk_in a a. because pllclk_in and pll_r eset signals have inpad, and pllpad_out has outpad, you do not have to add additional pads to your design input clock signal pll_reset active high reset if pll_reset is asserted, then clknet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. onn_offchip pll output this signal selects whether the pll will drive the internal clock network or be used off-chip. this is a static signal, not a dynamic signal. tied to gnd = outgoing signal drives internal gates. tied to vcc = outgoing signal used off-chip. clknet_out out to internal gates this signal bypasses the pll logic before driving the internal gates. note that this signal cannot be used in the same quadrant where the pll signal is used (pllclk_out). pllclk_out out from pll to internal gates this signal can drive the internal gates after going through the pll. for this to work, onn_offchip must be tied to gnd. pllpad_out out to off-chip this outgoing signal is used off-chip. for this to work, onn_offchip signal must be tied to vcc. lock_detect active high lock detection signal note: for simulation purposes, this signal gets asserted after 10 clock cycles. however, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the reset signal. table 19: dc input and output levels a inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lvttl n/a n/a -0.3 0.8 2.2 v ccio + 0.3 0.4 2.4 2.0 -2.0 lvcmos2 n/a n/a -0.3 0.7 1.7 v ccio + 0.3 0.7 1.7 2.0 -2.0 lvcmos18 n/a n/a -0.3 0.63 1.2 v ccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x v ccio 0.5 x v ccio v ccio + 0.5 0.1 x v ccio 0.9 x v ccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 v ccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 v ccio + 0.3 1.10 1.90 8 -8
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 19 note: all clk and ioctrl pins are clamped to the v ded rail. therefore, these pins can be driven up to v ded + 0.3 v. package thermal characteristics thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power di ssipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 150o c. to calculate the maximum power dissipation for a device package look up ja from table 20 , pick an appropriate t amax and use: p max = (150o c - t amax )/ ja a. the data provided in table 19 are jedec and pci specificat ions. quicklogic devices ei- ther meet or exceed these requirements. see preceding table 1 through table 14 and figure 1 through figure 17 for data specific to quicklogic i/os. table 20: package thermal characteristics package description ja (o c/w) @ various flow rates (m/sec) jc (o c/w) pin count package type 0 0.5 1 2 484 pbga 28.0 26.0 25.0 23.0 9.0 280 lf-pbga 18.5 17.0 15.5 14.0 7.0 208 pqfp 26.0 24.5 23.0 22.0 11.0
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 20 kv and kt graphs figure 18: voltage factor vs. supply voltage figure 19: temperature factor vs. operating temperature voltage factor vs. supply voltage 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 2.25 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 supply voltage (v) kv temperature factor vs. operating temperature 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 junction temperature c kt
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 21 power vs. operating frequency the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins note: to learn more about power consumption, please refer to application note #60.
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 22 power-up sequencing figure 20: power-up requirements the following requirements must be met when powering up a device (refer to figure 20 ): when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. deviation from this recommendation can cause perman ent damage to the device. v ccio must lead v cc when ramping the device. the power supply must be greater th an or equal to 400 s to reach v cc . ramping to v cc /v ccio before reaching 400 s can cause the device to behave improperly. voltage v ccio v cc (v ccio -v cc ) max 400 us v cc
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 23 joint test access group (jtag) figure 21: jtag block diagram microprocessors and application specific integrated circuits (asics) pose many design challenges, one problem being the accessibility of test points. the joint test access group (jtag) formed in response to this chal lenge, resulting in i eee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allo ws complete observation and control of the boundary pins of a jtag-compa tible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run three required tests along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 24 the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boun dary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (v ia the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan regist er to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data pa sses through the bypass register. th e bypass instruction allows users to test a device without passing through othe r devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device.
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 25 pin descriptions figure 22: i/o banks with relevant pins table 21: jtag pin descriptions pin function description tdi/rsi test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to v cc if unused trstb/rro active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag tdo/rco test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g)
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 26 table 22: dedicated pin descriptions pin function description gclk global clock network driver low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. i/o(a) input/output pin the i/o pin is a bi-directional pin, configurable to either an input- only, output-only, or bi-directional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quick works tool) provides the option of tying that pin to gnd, v cc, or tristate during programming. v cc power supply pin connect to 2.5 v supply v ccio (a) input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the a inside the parenthesis means that v ccio is located in bank a. every i/o pin in bank a will be tolerant of v ccio input signals and will output v ccio level signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. gnd ground pin connect to ground pllin pll clock input clock input for pll dedclk dedicated clock pin low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g. ram, flip flops). gndpll ground pin for pll connect to gnd inref(a) differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in table 19 for the appropriate standard. the a inside the parenthesis means that inref is located in bank a. this pin should be tied to gnd if not needed. pllout pll output pin dedicated pll output pin; otherwise, may be left unconnected ioctrl(a) highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parenthesis means that ioctrl is located in bank a. there is an internal pulldown resistor to ground on this pin. this pin should be tied to ground if it is not used. for backwards compatibility with eclipse, it can be tied to vcc or ground. if tied to vcc, it will draw no more than 20 a per ioctrl pin due to the pulldown resistor. (sheet 1 of 2)
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 27 vpump charge pump disable this pin disables the internal charge pump for lower static power operation. to disable the charge pump, connect vpump to 3.3 v. if the disable charge pump feature is not used, connect vpump to ground. for backwards compatibility with eclipse and eclipseplus devices, connect vpump to ground. vded voltage tolerance for clocks, jtag, and ioctrl/voltage drive for pllout and jtag pins this pin specifies the input voltage tolerance for clk, jtag, and ioctrl dedicated input pins, as well as the output voltage drive for pllout and jtag pins. if the plls are used, vded must be the same as v cc pll. for backwards compatibility with eclipse and eclipseplus devices, connect vded to 2.5 v. vccpll power supply pin for pll connect to 2.5 v supply or 3.3 v supply. for backwards compatibility with eclipse and eclipseplus devices, connect to 2.5 v. table 22: dedicated pin descriptions pin function description (sheet 2 of 2)
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 28 recommended unused pin term inations for the eclipse-e devices all unused, general purpose i/o pins can be tied to v cc , gnd, or hiz (high impedance) internally using the configuration editor. th is option is given in the botto m-right corner of the placement window. to use the placement editor, choose constraint > fix placement in the option pull- down menu of spde. the rest of the pins should be terminated at the board level in the manner presented in table 23 . 208 pqfp pinout diagram table 23: recommended unused pin terminations signal name recommended termination pllout a a. x represents a number. unused pll output pins must be connected to either v cc or gnd so that their associated input buffer never floats. utilized pll output pins that route the pll clock outside of the chip should not be tied to either v cc or gnd. ioctrl b b. y represents an aphabetical character. any unused pins of this type must be connected to either v cc or gnd. clk/pllin any unused clock pins should be connected to v cc or gnd. pllrst if a pll module is not used, then the associated pllrst must be connected to v cc , under normal operation use it as needed. inref if an i/o bank does not require the use of inref signal the pin should be connected to gnd. eclipse-e ql6325-e-6pq208c
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 29 208 pqfp pinout table table 24: 208 pqfp pinout table pqfp function pqfp function pqfp function pqfp function pqfp function 1 pllrst(3) 43 io(b) 85 io(d) 127 clk(5),pllin(3) 169 ioctrl(g) 2 v ccpll (3) 44 v ccio (b) 86 v cc 128 clk(6) 170 inref(g) 3 gnd 45 io(b) 87 io(d) 129 vded 171 ioctrl(g) 4 gnd 46 v cc 88 io(d) 130 clk(7) 172 io(g) 5 io(a) 47 io(b) 89 v cc 131 v cc 173 io(g) 6 io(a) 48 io(b) 90 io(d) 132 clk(8) 174 io(v) 7 io(a) 49 gnd 91 io(d) 133 tms 175 v cc 8 v ccio (a) 50 tdo 92 ioctrl(d) 134 io(f) 176 io(g) 9 io(a) 51 pllout(1) 93 inref(d) 135 io(f) 177 v ccio (g) 10 io(a) 52 gndpll(2) 94 ioctrl(d) 136 io(f) 178 gnd 11 ioctrl(a) 53 gnd 95 io(d) 137 gnd 179 io(g) 12 v cc 54 v ccpll (2) 96 io(d) 138 v ccio (f) 180 io(g) 13 inref(a) 55 pllrst(2) 97 io(d) 139 io(f) 181 io(g) 14 ioctrl(a) 56 v cc 98 v ccio (d) 140 io(f) 182 v cc 15 io(a) 57 io(c) 99 io(d) 141 io(f) 183 tck 16 io(a) 58 gnd 100 io(d) 142 io(f) 184 v cc 17 io(a) 59 io(c) 101 vpump 143 io(f) 185 io(h) 18 io(a) 60 v ccio (c) 102 pllout(0) 144 ioctrl(f) 186 io(h) 19 v ccio (a) 61 io(c) 103 gnd 145 inref(f) 187 io(h) 20 io(a) 62 io(c) 104 gndpll(1) 146 v cc 188 gnd 21 gnd 63 io(c) 105 pllrst(1) 147 ioctrl(f) 189 v ccio (h) 22 io(a) 64 io(c) 106 v ccpll (1) 148 io(f) 190 io(h) 23 tdi 65 io(c) 107 io(e) 149 io(f) 191 io(h) 24 clk(0) 66 io(c) 108 gnd 150 v ccio (f) 192 ioctrl(h) 25 clk(1) 67 ioctrl(c) 109 io(e) 151 io(f) 193 io(h) 26 v cc 68 inref(c) 110 io(e) 152 io(f) 194 inref(h) 27 clk(2),pllin(2) 69 ioctrl(c) 111 v ccio (e) 153 gnd 195 v cc 28 clk(3),pllin(1) 70 io(c) 112 io(e) 154 io(f) 196 ioctrl(h) 29 vded 71 io(c) 113 v cc 155 pllout(3) 197 io(h) 30 clk(4), dedclk,pllin(0) 72 v ccio (c) 114 io(e) 156 gndpll(0) 198 io(h) 31 io(b) 73 io(c) 115 io(e) 157 gnd 199 io(h) 32 io(b) 74 io(c) 116 io(e) 158 v ccpll (0) 200 io(h) 33 gnd 75 gnd 117 ioctrl(e) 159 pllrst(0) 201 io(h) 34 v ccio (b) 76 v cc 118 inref(e) 160 gnd 202 io(h) 35 io(b) 77 io(c) 119 ioctrl(e) 161 io(g) 203 v ccio (h) 36 io(b) 78 trstb 120 io(e) 162 v ccio (g) 204 gnd 37 io(b) 79 v cc 121 io(e) 163 io(g) 205 io(h) 38 io(b) 80 io(d) 122 v ccio (e) 164 io(g) 206 pllout(2) 39 ioctrl(b) 81 io(d) 123 gnd 165 v cc 207 gnd 40 inref(b) 82 io(d) 124 io(e) 166 io(g) 208 gndpll(3) 41 ioctrl(b) 83 gnd 125 io(e) 167 io(g) 42 io(b) 84 v ccio (d) 126 io(e) 168 io(g)
www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 30 280 pbga pinout diagram top bottom eclipse-e ql6325-e-6pt280c pin a1 corner
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 31 280 pbga pinout table table 25: 280 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 pllout<3> c10 clk<5> /pllin<3> e19 ioctrl k16 i/o r4 i/o u13 i/o a2 gndpll<0> c11 v ccio f1 inref k17 i/o r5 gnd u14 ioctrl a3 i/o c12 i/o f2 ioctrl k18 i/o r6 gnd u15 v ccio a4 i/o c13 i/o f3 i/o k19 trstb r7 v cc u16 i/o a5 i/o c14 i/o f4 i/o l1 i/o r8 v cc u17 tdo a6 ioctrl c15 v ccio f5 gnd l2 i/o r9 gnd u18 pllrst<2> a7 i/o c16 i/o f15 v cc l3 v ccio r10 gnd u19 i/o a8 i/o c17 i/o f16 ioctrl l4 i/o r11 v cc v1 pllout<2> a9 i/o c18 i/o f17 i/o l5 v cc r12 v cc v2 gndpll<3> a10 clk<7> c19 i/o f18 i/o l15 gnd r13 v cc v3 gnd a11 i/o d1 i/o f19 i/o l16 i/o r14 vded v4 i/o a12 i/o d2 i/o g1 i/o l17 v ccio r15 gnd v5 i/o a13 i/o d3 i/o g2 i/o l18 i/o r16 i/o v6 ioctrl a14 ioctrl d4 i/o g3 ioctrl l19 i/o r17 v ccio v7 i/o a15 i/o d5 i/o g4 i/o m1 i/o r18 i/o v8 i/o a16 i/o d6 i/o g5 v cc m2 i/o r19 i/o v9 i/o a17 i/o d7 i/o g15 v cc m3 i/o t1 i/o v10 clk<1> a18 pllrst<1> d8 i/o g16 i/o m4 i/o t2 i/o v11 clk<4> dedclk/pllin<0> a19 gnd d9 clk<8> g17 i/o m5 v cc t3 i/o v12 i/o b1 pllrst<0> d10 i/o g18 i/o m15 v cc t4 i/o v13 i/o b2 gnd d11 i/o g19 i/o m16 inref t5 i/o v14 inref b3 i/o d12 i/o h1 i/o m17 i/o t6 ioctrl v15 i/o b4 i/o d13 inref h2 i/o m18 i/o t7 i/o v16 i/o b5 i/o d14 i/o h3 i/o m19 i/o t8 i/o v17 i/o b6 inref d15 i/o h4 i/o n1 ioctrl t9 i/o v18 gndpll<2> b7 i/o d16 i/o h5 v cc n2 i/o t10 i/o v19 gnd b8 i/o d17 i/o h15 v cc n3 i/o t11 clk<3> /pllin<1> w1 gnd b9 tms d18 i/o h16 v cc n4 i/o t12 i/o w2 pllrst<3> b10 clk<6> d19 i/o h17 i/o n5 v cc t13 i/o w3 i/o b11 i/o e1 i/o h18 i/o n15 v cc t14 i/o w4 i/o b12 i/o e2 i/o h19 i/o n16 i/o t15 i/o w5 i/o b13 ioctrl e3 v ccio j1 i/o n17 i/o t16 i/o w6 i/o b14 i/o e4 i/o j2 i/o n18 ioctrl t17 v ccpll <2> w7 i/o b15 i/o e5 gnd j3 v ccio n19 ioctrl t18 i/o w8 i/o b16 i/o e6 v cc j4 i/o p1 i/o t19 i/o w9 tdi b17 v ccpll <1> e7 v cc j5 gnd p2 i/o u1 i/o w10 clk<2> /pllin<2> b18 gndpll<1> e8 vded j15 v cc p3 ioctrl u2 i/o w11 i/o b19 pllout<0> e9 v cc j16 i/o p4 inref u3 v ccpll <3> w12 i/o c1 i/o e10 gnd j17 v ccio p5 v cc u4 i/o w13 i/o c2 v ccpll <0> e11 gnd j18 i/o p15 gnd u5 v ccio w14 ioctrl c3 i/o e12 v cc j19 i/o p16 i/o u6 inref w15 i/o c4 i/o e13 v cc k1 v cc p17 i/o u7 i/o w16 i/o c5 v ccio e14 gnd k2 tck p18 i/o u8 i/o w17 i/o c6 ioctrl e15 vpump k3 i/o p19 i/o u9 v ccio w18 i/o c7 i/o e16 i/o k4 i/o r1 i/o u10 clk<0> w19 pllout<1> c8 i/o e17 v ccio k5 gnd r2 i/o u11 v ccio c9 v ccio e18 inref k15 gnd r3 v ccio u12 i/o www.quicklogic.com ? 2002 quicklogic corporation ql6325-e eclipse-e data sheet rev a preliminary 32 484 pbga pinout diagram top bottom eclipse-e ql6325-e-6ps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 ab aa pin a1 corner pin a1
? 2002 quicklogic corporation www.quicklogic.com ql6325-e eclipse-e data sheet rev a preliminary 33 484 pbga pinout table table 26: 484 pbga pinout table pbga function pbga function pbga function pbga function pbga function pbga function a1 i/o c1 i/o e1 ioctrl g1 i/o j1 i/o l1 clk<4> dedclk/pllin<0> a2 pllrst<3> c2 i/o e2 i/o g2 i/o j2 i/o l2 clk<0> a3 i/o c3 v ccpll <3> e3 i/o g3 i/o j3 i/o l3 clk<2>/pllin<2> a4 i/o c4 pllout<2> e4 i/o g4 i/o j4 i/o l4 i/o a5 i/o c5 i/o e5 i/o g5 i/o j5 i/o l5 i/o a6 i/o c6 i/o e6 i/o g6 i/o j6 i/o l6 i/o a7 i/o c7 i/o e7 n/c g7 gnd j7 i/o l7 gnd a8 ioctrl c8 i/o e8 i/o g8 i/o j8 v cc l8 gnd a9 i/o c9 ioctrl e9 i/o g9 i/o j9 gnd l9 gnd a10 n/c c10 i/o e10 i/o g10 i/o j10 v cc l10 gnd a11 n/c c11 i/o e11 v cc g11 i/o j11 v cc l11 gnd a12 tck c12 i/o e12 i/o g12 gnd j12 gnd l12 gnd a13 i/o c13 i/o e13 i/o g13 i/o j13 v cc l13 gnd a14 i/o c14 i/o e14 i/o g14 i/o j14 gnd l14 v cc a15 i/o c15 i/o e15 ioctrl g15 i/o j15 v cc l15 v cc a16 i/o c16 i/o e16 i/o g16 vpump j16 i/o l16 clk<6> a17 i/o c17 i/o e17 inref
